Fifteen periods of Si/Si_0.7Ge_0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si_0.7Ge_0.3 features the best crystal quality and no defects are observed. Stacked Si_0.7Ge_0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

A method for isochromatic determination in three-fringe photoelasticity is presented. It combines the phase-shifting method with cubic polynomial curve-fitting technology to eliminate the errors caused by color repetition. We perform a demonstration of the method on a circular disc subjected to compressive loading and an injection-molded cover with residual stresses. The test results compare well with the theoretical results.